The present invention relates to a vertical transistor in a trench geometry. More particularly, this invention relates to a process for fabricating a gate oxide of a vertical transistor which has a uniform thickness.
One of the consequences of the increased integration of transistors into the submicron regime is the decrease in the critical sizes of the transistors. An additional reduction of surface area is accomplished when the transistor is integrated in a vertical structure such as a trench or a stack. As the gate lengths are reduced, it becomes desirable to also reduce the thickness of the gate oxide as the simplest way to increase circuit speed. This is because, below about 0.5 xcexcm, velocity saturation prevents a scaled increase in drive current as gate length decreases. For high speed and best device performance, it is also desirable to produce gate oxides having a homogenous thickness.
Gate oxides are typically formed by thermal oxidation of a silicon substrate. A crystal structure, such as silicon, contains planes of atoms. These planes of atoms influence the properties and behavior of the material. For example, the oxidation rate (R) of a silicon substrate depends on the crystal orientation of the silicon substrate.
Accordingly, it has proven advantageous to identify the various planes within crystals such as silicon crystals. This has been done, by convention, using three numbers within brackets called Miller indices. The Miller indices that define a lattice plane are simply the reciprocals (cleared of fractions and common multipliers) of the intercepts of the plane with the x, y, and z axes of a rectangular or Cartesian coordinate system. Thus, the  less than 100 greater than  plane intercepts the x axis at one and has neither a y-axis intercept nor a z-axis intercept (the reciprocal of infinity is zero); the  less than 100 greater than  plane is parallel to the y-z plane. Another example is the  less than 110 greater than  plane, which intercepts both the x and y axes at one but has no z-axis intercept. The  less than 110 greater than  plane meets both the x-z plane and the y-z plane at a forty-five degree angle. Note, too, that the  less than 110 greater than  plane intercepts the  less than 100 greater than  plane at a forty-five degree angle.
As stated above, it is known that the thermal oxidation rate (R) of a silicon substrate depends on the crystal orientation of the silicon substrate. More specifically, at the oxidation temperatures of interest, the oxidation rate for a  less than 110 greater than  silicon surface orientation is faster than the rate for a  less than 100 greater than  silicon surface orientation (R less than 110 greater than  greater than R less than 100 greater than ). See E. Irene et al., xe2x80x9cSilicon Oxidation Studies: Silicon Orientation Effects on Thermal Oxidation,xe2x80x9d J. Electrochem. Soc""y 1253 (June 1986). FIG. 8 illustrates the conventional result: a thicker gate oxide 30 forms on the  less than 110 greater than  crystal plane than on the  less than 100 greater than  crystal plane and the oxide thickness is non-uniform.
It is also known that the introduction of nitrogen ions into a silicon substrate reduces the oxidation rate of the silicon substrate which has been implanted with the nitrogen ions. For example, in their article titled xe2x80x9cSimultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processingxe2x80x9d (IEEE Electron Device Letters, Vol. 16, No. 7, July 1995), Doyle et al. provide a process for implanting nitrogen ions into a planar silicon wafer to simultaneously form gate oxides of varying thickness on the wafer.
Unfortunately, the process of Doyle et al. does not address the need to form a gate oxide of a non-planar transistor having a substantially uniform thickness. In non-planar structures (i.e., those structures that do not present a completely uniform, uninterrupted, flat silicon surface), such as vertical trench or mesa structures, the silicon substrate consists of multiple crystal planes. Each of the crystal planes has a different oxidation rate. As a result, when the silicon substrate is oxidized to produce the gate oxide, the resulting gate oxide has a varying thickness corresponding to the different crystal planes. Therefore, there remains a need for a process of forming a gate oxide of substantially uniform thickness on non-planar structures.
To meet this and other needs, and in view of its purposes, the present invention provides a process of forming relatively thin gate oxides of substantially uniform thickness on non-planar structures. The invention more specifically provides a process for fabricating a gate oxide of a vertical transistor which has a substantially uniform thickness. In a first step of the process of the invention, a trench is formed in a substrate. The trench extends from a surface of the substrate and has a trench bottom and a trench side wall. The vertical trench side wall comprises  less than 100 greater than  crystal planes and  less than 110 greater than  crystal planes. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer into the  less than 110 greater than  crystal plane of the trench side wall, with the condition that the nitrogen ions are not implanted into the  less than 100 greater than  crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.
The present invention also encompasses the product of the process outlined above. Specifically, the invention provides a vertical transistor having a uniform and relatively thin gate oxide prepared by the foregoing process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.